1. Technical Field
The present inventions relate to systems, such as memory systems, in which commands are scheduled to be delivered during frequency mismatch bubbles.
2. Background Art
Various arrangements for memory chips in a memory system have been proposed. One such system is referred to as a Fully-Buffered Dual In-Line Memory Module (FBD or FBDIMM) system. FIG. 1 provides an example of an FBD system that includes a memory controller (host) 12, clock circuitry 14, a memory module 24, and a memory module 26. Memory module 24 includes a substrate 32 that supports a buffer 34 and eight synchronous dynamic random access memory devices (DRAMs) 38-1 . . . 38-8. (The number of DRAMs does not have to be eight.) Command, address, and write data (CAW) signals are provided from memory controller 12 to buffer 34 on conductors 42, and read data signals are provided from buffer 34 to memory controller 12 on conductors 44. The CAW are provided by buffer 34 to memory chips 38-1 . . . 38-8 and buffer 54, and read data is provided by memory chips 38-1 . . . 38-8 to buffer 34.
CAW signals are also provided from buffer 34 to buffer 54 through conductors 46 and read data signals are provided from buffer 54 to buffer 34 through conductors 48. The CAW are provided by buffer 54 to memory chips 58-1 . . . 58-8, supported by substrate 52, and read data is provided from memory chips 58-1 . . . 58-8 to buffer 54.
Memory controller 12 includes a scheduler 16 to schedule signals (including commands, address, and write data) to be provided through chip interface transmitters (FBD physical layer) 20. Clock (Clk) 1 is provided to scheduler 16 and clock gearing logic 18. Clock (Clk) 2 is provided to clock gearing logic 18, transmitting circuitry 20, and modules 24 and 26. Clock 2 is received by buffers 34 and 54 and passed on to the DRAM chips. Clock 2 has a higher frequency than clock 1. As an example, clock 2 may have a frequency of 533 MHz (1066 MHz double data rate (DDR)) and clock 1 may have a frequency of 400 MHz. This is a ratio of 4:3. Because of the difference in frequency, a frequency mismatch bubble between scheduled frames will occur in buffers 34 and 54 as shown in FIG. 3. Clock gearing logic 18 transitions signals from the frequency of clock 1 to the frequency of clock 2, and can determine the location of the bubbles and notify scheduler 16 of the temporal location of the bubbles through a beat rate signal. The temporal location of the bubbles may be expressed in various ways including identifying between which frames of scheduled commands the bubbles (BBL) will occur.
Transmitter circuitry 20 increases the frequency of the frames to 6 times that of clock 2 so that the CAW signals on conductors 42 have a frequency that is six times that of clock 2. However, buffer 34 reduces the frequency by a factor of six so that the signals from buffer 34 have the frequency of clock 2. Although the frequency is increased through transmitter circuitry 20, the number of conductors is reduced, and as the frequency is reduced through buffer 34, the number of conductors is increased.
The CAW signals are provided in frames that include three slots (the A slot, the B slot, and the C slot), each of which can hold a command, including operation commands and no operation (NOP) signals. The B and C slots can hold write data that is provided before or after the associated write command.
FIG. 2 shows frames 1, 2, . . . 6 as provided by scheduler 16 during cycles of clock 1 (the scheduler clock), referred to as cycles 1 , 2 . . . 6. Each frame includes A, B, and C slots. In FIG. 2, the A slot is shown as holding alternating RAS and CAS signals (RAS 1, CAS 1, RAS 2, CAS 2, RAS 3, CAS 3), although this is not always the case. Addresses are included in at least some of the RAS and CAS signals. The B and C slots are shown as including no operation (NOP) or write data (WD) signals in frames 2-6, but this is not required. In some implementations, it takes four frames of B and C slots to provide the write data for a write command. The designation frame 1 does not mean that it is the first frame from schedule 16. There may be other frames before frame 1.
In some FBD implementations, conductors 42 and 46 each have 10 lanes, and conductors 44 and 48 each have 14 lanes, with each lane having two conductors for differential signaling. With single ended signaling, each lane would have one conductor. While the frames are in conductors 42, the frames each are 10 lanes wide and 12 clock units in duration (six times a double data rate of clock 2 (DRAM clock)).
FIG. 3 illustrates the frames received by buffer 34 in which in the frequency of the signals is reduced by a factor of six as compared to the frames on conductors 42. The FBD frame clock is at the reduced frequency. A duration of a frame corresponds to one cycle of clock 2 (the DRAM clock). As illustrated, frames 1, 2, and 3 occur during cycles of clock 2 referred to as cycles 1, 2, and 3. The A slots of frames 1, 2, and 3 during cycles 1-3 include commands RAS 1, CAS 1, and RAS 2, and the B and C slots include NOP or write data. Because of the frequency of clock 2 is 4/3 times greater than that of clock 1, during cycle 4 of clock 2, signals scheduled by scheduler 16 for frame 4 are not provided until cycle 5 of clock 2. Cycle 4 is referred to as a bubble (BBL). Note that there is not a similar bubble in FIG. 2. The A slots of frames 4, 5, and 6 in cycles 5, 6, and 7 include CAS 2, RAS 3, and CAS 3 commands, and slots B and C include NOP or write data signals. Cycle 8 is also a bubble.
According to the FBD specification, the contents in B and C slots get delivered in the next DRAM cycle after delivering the command in the A slot. Accordingly, the contents in B and C slots and next frame's A slot gets delivered in same cycle to the DRAM. For example, during one clock cycle, buffer 34 provides the contents of the A slot (CAS 1) of frame 2 and the contents of the B and C slots of frame 1 to DRAMs 38-1 . . . 38-8 and buffer 54. During the next cycle, buffer 34 provides the contents of the A slot (RAS 2) of frame 3 and the contents of the B and C slots of frame 2 to DRAMs 38-1 . . . 38-8 and buffer 54.
The DRAMs may be double data rate 2 (DDR 2) DRAMs on some other type of DRAMs. The signaling between memory buffer 34 and DRAMs 38-1 . . . 38-8 may be like traditional DDR 2 signaling. There may be more or less than eight DRAM chips in the modules. DRAMs may be on only one side or both sides of the substrate. Multiple modules may be in series and/or parallel. A system may include one or more than one memory channel.
Memory controllers have been used in chipset hubs and in a chip that includes processor cores. Some computer systems include wireless transmitter and receiver circuits.